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HA4314B
Data Sheet December 8, 2006 FN3679.11
400MHz, 4x1 Video Crosspoint Switch
The HA4314B is a very wide bandwidth 4 x 1 crosspoint switch ideal for professional video switching, HDTV, computer monitor routing, and other high performance applications. The circuit features very low power dissipation (105mW Enabled, 4mW Disabled), excellent differential gain and phase, and very high off isolation. When disabled, the output is switched to a high impedance state, making the HA4314B ideal for routing matrix equipment. The HA4314B requires no external current source, and features fast switching and symmetric slew rates. For a 4x1 crosspoint with Tally outputs (channel indicators) or with synchronous control signals, please refer to the HA4404B and HA4344B data sheets, respectively. For audio channels requiring larger signal swings, please refer to the CD22M3494 (16x8) data sheet.
Features
* Low Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 105mW * Symmetrical Slew Rates. . . . . . . . . . . . . . . . . . . . . 1400V/s * 0.1dB Gain Flatness . . . . . . . . . . . . . . . . . . . . . . . . . 100MHz * -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400MHz * Off Isolation (100MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 70dB * Crosstalk Rejection (30MHz) . . . . . . . . . . . . . . . . . . . . . 80dB * Differential Gain and Phase . . . . . . . . . 0.01%/0.01 Degrees * High ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2000V * TTL Compatible Control Inputs * Improved Replacement for GX4314 and GX4314L * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Professional Video Switching and Routing * HDTV
Ordering Information
PART NUMBER HA4314BCA PART MARKING HA4314BCA TEMP. RANGE (C) 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 PACKAGE PKG. DWG. #
* Computer Graphics * RF Switching and Routing * PCM Data Routing
16 Ld QSOP M16.15A 16 Ld QSOP M16.15A (Pb-free) 14 Ld SOIC M14.15 14 Ld SOIC M14.15 (Pb-free) 14 Ld PDIP E14.3
HA4314BCAZ* HA4314BCAZ (Note) HA4314BCB* HA4314BCB
Truth Table
CS 0 0 0 0 1 A1 0 0 1 1 X A0 0 1 0 1 X OUT IN0 IN1 IN2 IN3 HIGH - Z
HA4314BCBZ* 4314BCBZ (Note) HA4314BCP HA4314BCP
HA4314BCPZ HA4314BCPZ (Note) *Add "96" suffix for tape and reel.
14 Ld PDIP* E14.3 (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HA4314B
T
Pinouts
HA4314B (16 LD QSOP) TOP VIEW
IN0 GND IN1 GND IN2 GND IN3 GND 1 2 3 4 5 6 7 8 16 V+ 15 A0 14 A1 13 CS 12 OUT 11 NOTE 10 NOTE 9 VIN0 GND IN1 GND IN2 GND IN3
HA4314B (14 LD PDIP, SOIC) TOP VIEW
1 2 3 4 5 6 7 14 V+ 13 A0 12 A1 11 CS 10 OUT 9 NC 8 V-
NOTE: These pins must be left floating or connected to ground
Absolute Maximum Ratings
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Digital Input Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Analog Input Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2000V
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (C/W)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 QSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . +175C Maximum Junction Temperature (Plastic Package) . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . -65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300C (SOIC and QSOP - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
Electrical Specifications
PARAMETER
VSUPPLY = 5V, RL = 10k, VCS = 0.8V, Unless Otherwise Specified TEST CONDITIONS (NOTE 4) TEMP. (C) MIN TYP MAX UNITS
DC SUPPLY CHARACTERISTICS Supply Voltage Supply Current (VOUT = 0V) VCS = 0.8V VCS = 0.8V VCS = 2.0V VCS = 2.0V ANALOG DC CHARACTERISTICS Output Voltage Swing without Clipping VOUT = VIN VIO 20mV +25, +70 0 Output Current Input Bias Current Output Offset Voltage Output Offset Voltage Drift (Note 3) SWITCHING CHARACTERISTICS Turn-On Time +25 160 ns Full Full Full Full 2.7 2.4 15 -10 2.8 2.5 20 30 25 50 10 50 V V mA A mV V/C Full +25, +70 0 +25, +70 0 4.5 5.0 10.5 400 400 5.5 13 15.5 450 580 V mA mA A A
2
HA4314B
Electrical Specifications
PARAMETER Turn-Off Time Output Glitch During Switching DIGITAL DC CHARACTERISTICS Input Logic High Voltage Input Logic Low Voltage Input Current AC CHARACTERISTICS Insertion Loss 1VP-P +25 Full Channel-to-Channel Insertion Loss Match -3dB Bandwidth RS = 50, CL = 10pF RS = 20, CL = 20pF RS = 16, CL = 36pF RS = 13, CL = 49pF 0.1dB Flat Bandwidth RS = 50, CL = 10pF RS = 20, CL = 20pF RS = 16, CL = 36pF RS = 13, CL = 49pF Input Resistance Input Capacitance Enabled Output Resistance Disabled Output Capacitance Differential Gain Differential Phase Off Isolation Crosstalk Rejection Slew Rate (1.5VP-P, +SR/-SR) VCS = 2.0V 4.43MHz, (Note 3) 4.43MHz, (Note 3) 1VP-P, 100MHz, VCS = 2.0V, RL = 10 1VP-P, 30MHz RS = 50, CL = 10pF RS = 20, CL = 20pF RS = 16, CL = 36pF RS = 13, CL = 49pF Total Harmonic Distortion Disabled Output Resistance NOTES: 3. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-lot variation. 4. Units are 100% tested at +25C; Guaranteed but not tested at 0C and +70C. 10MHz, RL = 1k, (Note 3) VCS = 2.0V Full +25 +25 +25 +25 +25 +25 +25 +25 Full Full Full Full +25 +25 Full Full +25 +25 +25 +25 Full Full 200 0.055 0.07 0.004 400 280 140 110 100 100 85 75 400 1.5 15 2.5 0.01 0.01 70 80 1425/1450 1010/1010 725/750 600/650 0.01 12 0.063 0.08 0.006 0.02 0.02 0.1 dB dB dB MHz MHz MHz MHz MHz MHz MHz MHz k pF pF % Degrees dB dB V/s V/s V/s V/s % M 0V to 4V Full Full Full 2 -2 0.8 2 V V A VSUPPLY = 5V, RL = 10k, VCS = 0.8V, Unless Otherwise Specified (Continued) TEST CONDITIONS (NOTE 4) TEMP. (C) +25 +25 MIN TYP 320 10 MAX UNITS ns mV
3
HA4314B AC Test Circuit
500 400 510
PC Board Layout
The frequency response of this circuit depends greatly on the care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must!
75 VOUT HFA1100
HA4314 VIN 75 CX RS
+ 10k
Attention should be given to decoupling the power supplies. A large value (10F) tantalum in parallel with a small value (0.1F) chip capacitor works well in most cases. Keep input and output traces as short as possible, because trace inductance and capacitance can easily become the performance limiting items.
NOTE:
CL = CX + Test Fixture Capacitance.
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HA4314B Application Information
General
The HA4314B is a 4x1 crosspoint switch that is ideal for the matrix element of high performance switchers and routers. This crosspoint's low input capacitance and high input resistance provide excellent video terminations when used with an external 75 resistor. Nevertheless, if several HA4314B inputs are connected together, the use of an input buffer should be considered (see Figure 1). This crosspoint contains no feedback or gain setting resistors, so the output is a true high impedance load when the IC is disabled (CS = 1).
Switcher/Router Applications
Figure 1 illustrates one possible implementation of a wideband, low power, 4x4 switcher/router utilizing the HA4314B for the switch matrix. A 4x4 switcher/router allows any of the four outputs to be driven by any one of the four inputs (e.g., each of the four inputs may connect to a different output, or an input may connect to multiple outputs). This application utilizes the HA4600 (video buffer with output disable) for the input buffer, the HA4314B as the switch matrix, and the HFA1112 (programmable gain buffer) as the gain of two output driver. Figure 2 details a 16 x 1 switcher (basically a 16:1 mux) which uses the HA4201 (1x1 crosspoint) and the HA4314B in a cascaded stage configuration to minimize capacitive loading at each output node, thus increasing system bandwidth.
Ground Connections
All GND pins are connected to a common point on the die, so any one of them will suffice as the functional GND connection. For the best isolation and crosstalk rejection, however, all GND pins must connect to the GND plane.
Power Up Considerations
No signals should be applied to the analog or digital inputs before the power supplies are activated. Latch-up may occur if the inputs are driven at the time of power up. To prevent latch-up, the input currents during power up must not exceed the values listed in the Absolute Maximum Ratings.
Frequency Response
Most applications utilizing the HA4314B require a series output resistor, RS, to tune the response for the specific load capacitance, CL, driven. Bandwidth and slew rate degrade as CL increases (as shown in the Electrical Specifications), so give careful consideration to component placement to minimize trace length. In big matrix configurations where CL is large, better frequency response is obtained by cascading two levels of crosspoints in the case of multiplexed outputs (see Figure 2), or distributing the load between two drivers if CL is due to bussing and subsequent stage input capacitance.
Intersil's Crosspoint Family
Intersil offers a variety of 4x1 and 1x1 crosspoint switches. In addition to the HA4314B, the 4x1 family includes the HA4404 and HA4344. The HA4404 is a 16 lead device with Tally outputs to indicate the selected channel. The HA4344 is a 16 lead crosspoint with synchronized control lines (A0, A1, CS). With synchronization, the control information for the next channel switch can be loaded into the crosspoint without affecting the current state. On a subsequent clock edge the stored control state effects the desired channel switch. The 1 x 1 family is comprised of the HA4201 and HA4600. They are essentially similar devices, but the HA4201 includes a Tally output (enable indicator). The 1x1s are useful as high performance video input buffers, or in a switch matrix requiring very high off isolation.
Control Signals
CS - This is a TTL/CMOS compatible, active low Chip Select input. When driven high, CS forces the output to a true high impedance state and reduces the power dissipation by a factor of 25. The CS input has no on-chip pull-down resistor, so it must be connected to a logic low (recommend GND) if the enable function isn't utilized. A0, A1 - These are binary coded, TTL/CMOS compatible address inputs that select which one of the four inputs connect to the crosspoint output.
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HA4314B
INPUT BUFFERS +5V EN SOURCE 0 75 OUT HA4600 RS IN0 SOURCE 1 75 HA4314 CS IN0
SWITCH MATRIX
IN0 HA4314 CS
IN0 HA4314 CS
HA4314 CS
SOURCE 2 75 +5V EN SOURCE 3 75 OUT IN3
RS OUT IN3
RS OUT IN3
RS OUT IN3
RS
X2 75
X2 75
X2 75
OUT0
OUT1
OUT2
OUT3
FIGURE 1. 4x4 SWITCHER/ROUTER APPLICATION
6
-+
-+
-+
-+
OUT RS HA4600 OUTPUT BUFFERS (HFA1112 OR HFA1115)
X2 75
HA4314B
HA4314 SOURCE0 75 IN0 IN1 IN2 SOURCE3 75 RS OUT SOURCE4 75 IN0 IN1 IN2 SOURCE7 75 HA4314 SOURCE8 75 IN0 IN1 IN2 SOURCE11 75 RS OUT SOURCE12 75 IN0 IN1 IN2 SOURCE15 75 HA4314 SWITCHING MATRIX ISOLATION MUX OUTPUT BUFFER IN3 CS OUT RS EN RS IN3 CS 1/4 CD74HCT00 SEL8:11 SEL12:15 IN3 HFA1112 OR HFA1115 75 + X2 CS OUT RS EN RS IN3 CS 1/4 CD74HCT00 SEL0:3 SEL4:7
HA4201
OUT
HA4201
FIGURE 2. 16x1 SWITCHER APPLICATION
Typical Performance Curves
1.0
VSUPPLY = 5V, TA = +25C, RL = 10k, Unless Otherwise Specified
IN1 = +250mV IN3 = 0V A0 = +3V
A1 (V) OUTPUT VOLTAGE (mV) TIME (5ns/DIV.)
0.75 OUTPUT VOLTAGE (V) 0.5 0.25 0 -0.25 -0.5 -0.75 -1.0
2.4 1.6 0.8 0 250 125 0
TIME (200ns/DIV.)
FIGURE 3. LARGE SIGNAL PULSE RESPONSE
FIGURE 4. CHANNEL-TO-CHANNEL SWITCHING RESPONSE
7
HA4314B Typical Performance Curves
12 9 6 GAIN (dB) 3 0 -3 -6 -9 -12 1 CL = 20pF CL = 36pF CL = 49pF 10 FREQUENCY (MHz) 100 500 CL = 10pF GAIN (dB) VIN = 1VP-P
VSUPPLY = 5V, TA = +25C, RL = 10k, Unless Otherwise Specified (Continued)
VIN = 1VP-P 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 1 CL = 20pF CL = 49pF CL = 36pF CL = 10pF CL = 20pF
10 FREQUENCY (MHz)
100
200
FIGURE 5. FREQUENCY RESPONSE
FIGURE 6. GAIN FLATNESS
-40 -50
VIN = 1VP-P RL = 10k OFF ISOLATION (dB)
-10 -20 -30 -40 -50 -60 -70 -80
VIN = 1VP-P RL = 10
CROSSTALK (dB)
-60 -70 PDIP -80 -90 SOIC -100 -110 -120 0.6 1 10 FREQUENCY (MHz) 100 200 SSOP
SOIC
PDIP -90
SSOP
-100 0.3 1 10 FREQUENCY (MHz) 100 200
FIGURE 7. ALL HOSTILE CROSSTALK REJECTION
FIGURE 8. ALL HOSTILE OFF ISOLATION
0.2 TOTAL HARMONIC DISTORTION (%) VIN = 1VP-P RL = 1k 0.15 INPUT CAPACITANCE (pF)
3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 CH 1 CH 2 1 10 FREQUENCY (MHz) 100 500 CH 3 CH 0
0.1
0.05
0 10
1.4 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100
FIGURE 9. TOTAL HARMONIC DISTORTION vs FREQUENCY
FIGURE 10. INPUT CAPACITANCE vs FREQUENCY
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HA4314B Die Characteristics
DIE DIMENSIONS: 65 mils x 118 mils x 19 mils 1640m x 3000m x 483m METALLIZATION: Type: Metal 1: AlCu (1%)/TiW Thickness: Metal 1: 6kA 0.8kA Type: Metal 2: AlCu (1%) Thickness: Metal 2: 16kA 1.1kA PASSIVATION: Type: Nitride Thickness: 4kA 0.5kA TRANSISTOR COUNT: 200 SUBSTRATE POTENTIAL (POWERED UP): V-
Metallization Mask Layout
HA4314B
GND IN0 NC V+
IN1
A0
NC
A1
GND
CS
NC
OUT
IN2
NC
GND
NC
IN3
GND
NC
V-
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HA4314B Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 14 2.93
10
HA4314B Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 5.80 0.25 0.40 14 0o MAX 1.75 0.25 0.51 0.25 8.75 4.00 6.20 0.50 1.27 8o NOTES 9 3 4 5 6 7 Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497 0.2284 0.0099 0.016 14 0o
MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574 0.2440 0.0196 0.050 8o
A1 B C D E e
C
A1 0.10(0.004)
e
B 0.25(0.010) M C AM BS
0.050 BSC
1.27 BSC
H h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
11
HA4314B Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP)
N INDEX AREA E -B1 2 3 0.25 0.010 h x 45 L GAUGE PLANE H 0.25(0.010) M BM
M16.15A
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150" WIDE BODY) INCHES SYMBOL A A1
SEATING PLANE -AD -CA
MILLIMETERS MIN 1.55 0.102 1.40 0.20 0.191 4.80 3.81 MAX 1.73 0.249 1.55 0.31 0.249 4.98 3.99 NOTES 9 3 4 5 6 7 8 Rev. 2 6/04
MIN 0.061 0.004 0.055 0.008 0.0075 0.189 0.150
MAX 0.068 0.0098 0.061 0.012 0.0098 0.196 0.157
A2 B C D
A1 0.10(0.004) A2 C
E e H h L
e
B 0.17(0.007) M C AM BS
0.025 BSC 0.230 0.010 0.016 16 0 8 0.244 0.016 0.035
0.635 BSC 5.84 0.25 0.41 16 0 6.20 0.41 0.89
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
N
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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